Specman
Specman is an EDA tool that provides advanced automated functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the e Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification.[1][2]
The Specman tool itself does not include an HDL simulator (for design languages such as VHDL or Verilog.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. Specman is a feature of Cadence's new Xcelium simulator, where tighter product integration offers both faster runtime performance and debugs capabilities not available with other HDL simulators. In principle, Specman can co-simulate with any HDL simulator supporting standard PLI or VHPI interface, such as Synopsys's VCS, or Mentor's Questa.
History
[edit]Specman was originally developed at Verisity, an Israel-based company, which was acquired by Cadence on April 7, 2005.
It is now part of Cadence's functional verification suite.
References
[edit]- ↑ IONIŢĂ, F; CARP, M (2017). "SPECMAN-UVM BASED TEST BENCH". Bulletin of the Transilvania University of Braşov. 10 (2): 175–180.
- ↑ Tietz, Christoph; Stieber, Sebastian; Charaf, Najdet; Göhringer, Diana (2022). "A Framework for the Execution of Python Tests in SystemC and Specman Testbenches" (PDF). Design and Verification Conference.
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